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19-2640; Rev 0; 10/02
KIT ATION EVALU ILABLE AVA
1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators
General Description Features
o 6A PWM Step-Down Regulator with 95% Efficiency o 1MHz/500kHz Switching for Small External Components o 0.76in2 Complete 6A Regulator Footprint o External Components' Height <3mm o 1% Output Accuracy over Load and Line o Operate from 2.6V to 5.5V Supply o Operate from 2.5V Input with VCC at 3.3V/5V o Preset Output Voltage of 1.8V or 2.5V o Adjustable Output from 0.8V to 85% of Input o Voltage Margining: 4% (MAX1945R) or 9% (MAX1945S) o Synchronize to External Clock o SYNCOUT Provides 180-Degree Out-of-Phase Clock Output o All-Ceramic or Electrolytic Capacitor Designs
MAX1945R/MAX1945S
The MAX1945R/MAX1945S high-efficiency pulse-width modulation (PWM) switching regulators deliver up to 6A of output current. The devices operate from an input supply range of 2.6V to 5.5V and provide selectable output voltages of 1.8V, 2.5V, and adjustable output voltages from 0.8V to 85% of the supply voltage. With VCC at 3.3V/5V, the input voltage can be as low as 2.25V. The MAX1945R/MAX1945S are ideal for onboard post-regulation applications. Total output voltage error is less than 1% over load, line, and temperature. The MAX1945R/MAX1945S operate at a selectable fixed frequency (500kHz or 1MHz) or can be synchronized to an external clock (400kHz to 1.2MHz). The high operating frequency minimizes the size of external components. The high bandwidth of the internal error amplifier provides excellent transient response. The MAX1945R/MAX1945S have internal dual N-channel MOSFETs to lower heat dissipation at heavy loads. Two MAX1945R/MAX1945Ss can operate 180 degrees outof-phase of each other to minimize input capacitance. The devices provide output voltage margining for board-level testing. The MAX1945R provides a 4% voltage margining. The MAX1945S provides a 9% voltage margining. The MAX1945R/MAX1945S are available in 28-pin TSSOP-EP packages and are specified over the -40C to +85C industrial temperature range. An evaluation kit is available to speed designs.
Ordering Information
PART MAX1945REUI MAX1945SEUI TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 28 TSSOP-EP* 28 TSSOP-EP
Applications
Low-Voltage, High-Density Distributed Power Supplies ASIC, CPU, and DSP Core Voltages RAM Power Supply Base Station, Telecom, and Networking Equipment Power Supplies Server and Notebook Power Supplies
*EP = Exposed pad.
Typical Operating Circuit
INPUT 2.6V TO 5.5V
BST IN VDD VCC MAX1945R MAX1946S PGND LX
OUTPUT 0.8V TO 0.85 x VIN, 6A
VOLTAGE MARGINING ON/OFF
CTL1 CTL2 SYNC
FB SYNCOUT 180 OUT-OF-PHASE REF GND
SYNCHRONIZATION CLOCK
COMP FBSEL
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators MAX1945R/MAX1945S
ABSOLUTE MAXIMUM RATINGS
CTL1, CTL2, IN, SYNC, VCC, VDD to GND ...............-0.3V to +6V SYNCOUT, COMP, FB, FBSEL, REF to GND ............................................-0.3V to (VCC + 0.3V) LX Current (Note 1) .....................................................-9A to +9A BST to LX..................................................................-0.3V to +6V PGND to GND .......................................................-0.3V to +0.3V Continuous Power Dissipation (TA = +85C) (derate 23.8mW/C above +70C) .............................1191mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:
LX has internal clamp diodes to PGND and IN. Applications that forward bias these diodes should take care not to exceed the IC's package power dissipation limits.
ELECTRICAL CHARACTERISTICS
(VIN = VCC = VCTL1 = VCTL2 = VDD = 3.3V, SYNC = GND, FBSEL = High-Z, VFB = 0.7V, CREF = 0.22F, TA = 0C to +85C, unless otherwise noted. Typical values are at +25C.)
PARAMETER IN/VCC Input Voltage IN Supply Current VCC Supply Current VDD Supply Current Total Shutdown Current from IN, VCC, and VDD VCC Undervoltage Lockout Threshold VDD VDD Shutdown Supply Current BST BST Shutdown Supply Current REF REF Voltage REF Shutdown Resistance COMP FBSEL = High-Z COMP Transconductance VLOW_
CLAMP
SYMBOL VIN IIN ICC IDD ITOTAL VUVLO
CONDITIONS
MIN 2.6
TYP
MAX 5.5
UNITS V mA mA mA A V
SYNC = VCC (1MHz), no load SYNC = VCC (1MHz) SYNC = VCC (1MHz)
VIN = 3.3V VIN = 5.5V VCC = 3.3V VCC = 5.5V VDD = 3.3V VDD = 5.5V
10 48 2 3 4 9
20 3 6
VIN = VCC = VDD = VBST - VLX = 5.5V, CTL1 = CTL2 = GND When LX starts/stops switching VCC rising VCC falling 2.20 2.40 2.35
500 2.55
VIN = VDD = VBST = 5.5V, VLX = 5.5V or 0, CTL1 = CTL2 = GND
10
A
IBST
VIN = VDD = VBST = 5.5V, VLX = 5.5V or 0, CTL1 = CTL2 = GND IREF = 0, VIN = 2.6V to 5.5V From REF to GND, CTL1 = CTL2 = GND 30 13.3 9.6 0.5 1.90 1.97 2.00 10 55 24.4 17.6 0.8 2.15 10
10
A
VREF
2.04 100 85 37.8 27.2 1.1 2.40 100
V
From FB to COMP, VCOMP = 1.25V
FBSEL = GND FBSEL = VCC
S
COMP Clamp Voltage Low COMP Clamp Voltage High COMP Shutdown Resistance
VIN = 2.6V to 5.5V, VFB = 0.9V VIN = 2.6V to 5.5V, VFB = 0.7V From COMP to GND, CTL1 = CTL2 = GND
V V
VHIGH_
CLAMP
2
_______________________________________________________________________________________
1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VCC = VCTL1 = VCTL2 = VDD = 3.3V, SYNC = GND, FBSEL = High-Z, VFB = 0.7V, CREF = 0.22F, TA = 0C to +85C, unless otherwise noted. Typical values are at +25C.)
PARAMETER FB FBSEL = GND FB Regulation Voltage (Error Amp Only) Maximum Output Current VFB IFB_OUT VCOMP = 1V to 2V, VIN = 2.6V to 5.5V FBSEL = VCC FBSEL = High-Z CTL1 = VCC, CTL2 = VCC MAX1945R, VCOMP = 1V to 2V, VIN = 2.6V to 5.5V FB Voltage Margining Output (Error Amp Only) VMARGIN_ MAX1945S, VCOMP = 1V to 2V, VIN = 2.6V to 5.5V CTL1 = GND, CTL2 = VCC CTL1 = VCC, CTL2 = GND CTL1 = VCC, CTL2 = VCC CTL1 = GND, CTL2 = VCC CTL1 = VCC, CTL2 = GND FB Input Resistance FB Input Bias Current LX LX On-Resistance High LX On-Resistance Low LX Current-Sense Transresistance LX Current-Limit Threshold LX Leakage Current LX Switching Frequency LX Minimum Off-Time LX Maximum Duty Cycle ILEAK_LX fSW tOFF RON_HIGH_ VIN = VBST - VLX = 3.3V LX VIN = VBST - VLX = 2.6V RON_LOW_
LX
MAX1945R/MAX1945S
SYMBOL
CONDITIONS
MIN 1.782 2.475 0.792 6 -1 3 -5 -1 8 -10 25
TYP 1.800 2.500 0.800
MAX 1.818 2.525 0.808
UNITS
V A
VIN = 3.3V, VOUT = 1.8V, L = 1H
+1 5 -3 % +1 10 -8 50 0.01 26 30 26 30 100 0.10 43 50 43 50 65 12.8 -2 100 k A
FB to GND, FBSEL = GND, or VFB = 1.8V, or FBSEL = VCC, or VFB = 2.5V FBSEL = High-Z, VFB = 0.7V
m m m A A MHz kHz ns %
VIN = 3.3V VIN = 2.6V From LX to COMP Duty cycle =100%, VIN = 2.6V/3.3V/5.5V VIN = 5.5V, CTL1 = CTL2 = GND VIN = 2.6V/3.3V VIN = 2.6V/3.3V VIN = 2.6V/3.3V SYNC = GND SYNC = VCC 90 80 High side Low side VLX = 5.5V LX = GND SYNC = VCC SYNC = GND -100 0.8 400 43 8.0 -6
54 10.4 -4
1.0 500 120
1.2 600 170
_______________________________________________________________________________________
3
1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators MAX1945R/MAX1945S
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VCC = VCTL1 = VCTL2 = VDD = 3.3V, SYNC = GND, FBSEL = High-Z, VFB = 0.7V, CREF = 0.22F, TA = 0C to +85C, unless otherwise noted. Typical values are at +25C.)
PARAMETER LX Minimum Duty Cycle RMS LX Output Current FBSEL FBSEL Input Threshold 1.8V Where 1.8V feedback switches in and out, VCC = 2.6V/3.3V/5.5V Where 2.5V feedback switches in and out, VCC = 2.6V/3.3V/5.5V ILOW_
FBSEL
SYMBOL
CONDITIONS VIN = 2.6V/3.3V SYNC = GND SYNC = VCC
MIN
TYP 5 10
MAX 16 6
UNITS % A
FBSEL rising FBSEL falling FBSEL rising FBSEL falling VCC 0.22 -50 0.08
0.16 0.14 VCC 0.14 VCC 0.16 -20 20
0.22 V VCC 0.08
FBSEL Input Threshold 2.5V
V
FBSEL Input Current Low FBSEL Input Current High CTL1 /CTL2 CTL1/CTL2 Input Threshold CTL1/CTL2 Input Current Soft-Start Period Time from Nominal to Margin High Time from Nominal to Margin Low SYNC SYNC Capture Range SYNC Pulse Width SYNC Input Threshold SYNC Input Current SYNCOUT SYNCOUT Frequency Range
FBSEL = GND FBSEL = VCC
A 50 A
IHIGH_
FBSEL
VIL_CTL_ VIH_CTL_ IIL_CTL_ IIH_CTL_ tHIGH_4% tHIGH_9% tLOW_4% tLOW_9%
VIN = 2.6V to 5.5V VCTL1 or VCTL2 = 0 or 5.5V, VIN = 5.5V Time required for output to ramp up +4% +9% -4% -9% VIN = 2.6V to 5.5V
0.4 -1 -1 2.9
0.95 1.0 1.6 +1 +1 3.7 160 360 450 1000 4.5
V A ms s s
0.4 250 0.40 -1 0.4 VCC 0.4 VCC 0.05 0.95 1.0
1.2
MHz ns
tLO, tHI VIL_SYNC VIH_SYNC IIL, IIH fSYNCOUT VOH_SYNC
OUT
VIN = 2.6V to 5.5V VIN = 2.6V to 5.5V VSYNC = 0 or 5.5V, VIN = 5.5V VCC = 2.6V to 5.5V
1.6 +1 1.2
V A MHz
SYNCOUT Output Voltage
VOL_SYNC
OUT
ISYNCOUT = 1mA, VCC = 2.6V to 5.5V
V 0.05 0.40
4
_______________________________________________________________________________________
1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VCC = VCTL1 = VCTL2 = VDD = 3.3V, SYNC = GND, FBSEL = High-Z, VFB = 0.7V, CREF = 0.22F, TA = 0C to +85C, unless otherwise noted. Typical values are at +25C.)
PARAMETER THERMAL SHUTDOWN Thermal-Shutdown Hysteresis Thermal-Shutdown Threshold When LX stops switching 20 165 C C SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1945R/MAX1945S
ELECTRICAL CHARACTERISTICS
(VIN = VCC = VCTL1 = VCTL2 = VDD = 3.3V, SYNC = GND, FBSEL = High-Z, VFB = 0.7V, CREF = 0.22F, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER IN/VCC Input Voltage IN Supply Current VCC Supply Current VDD Supply Current Total Shutdown Current from IN, VCC, and VDD VCC Undervoltage Lockout Threshold VDD VDD Shutdown Supply Current BST BST Shutdown Supply Current REF REF Voltage REF Shutdown Resistance COMP FBSEL = High-Z COMP Transconductance VLOW_
CLAMP
SYMBOL VIN IIN ICC IDD ITOTAL VUVLO
CONDITIONS
MIN 2.6
TYP
MAX 5.5 20 4 6 500 2.55
UNITS V mA mA mA A V
SYNC = VCC (1MHz), no load SYNC = VCC (1MHz) SYNC = VCC (1MHz)
VIN = 3.3V VCC = 3.3V VDD = 3.3V
VIN = VCC = VDD = VBST - VLX = 5.5V, CTL1 = CTL2 = GND When LX starts/stops switching VCC rising VCC falling 2.20
IVDD
VIN = VDD = VBST = 5.5V, VLX = 5.5V or 0, CTL1 = CTL2 = GND
10
A
IBST
VIN = VDD = VBST = 5.5V, VLX = 5.5V or 0, CTL1 = CTL2 = GND IREF = 0, VIN = 2.6V to 5.5V From REF to GND, CTL1 = CTL2 = GND 30 13.3 9.6 0.5 1.90 1.96
10
A
VREF
2.04 100 85 37.8 27.2 1.1 2.40 100
V
From FB to COMP, VCOMP = 1.25V
FBSEL = GND FBSEL = VCC
S
COMP Clamp Voltage Low COMP Clamp Voltage High COMP Shutdown Resistance
VIN = 2.6V to 5.5V, VFB = 0.9V VIN = 2.6V to 5.5V, VFB = 0.7V From COMP to GND, CTL1 = CTL2 = GND
V V
VHIGH_
CLAMP
_______________________________________________________________________________________
5
1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators MAX1945R/MAX1945S
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VCC = VCTL1 = VCTL2 = VDD = 3.3V, SYNC = GND, FBSEL = High-Z, VFB = 0.7V, CREF = 0.22F, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER FB FBSEL = GND FB Regulation Voltage (Error Amp Only) Maximum Output Current VFB IFB_OUT VCOMP = 1V to 2V, VIN = 2.6V to 5.5V FBSEL = VCC FBSEL = High-Z CTL1 = VCC, CTL2 = VCC MAX1945R, VCOMP = 1V to 2V, VIN = 2.6V to 5.5V FB Voltage Margining Output (Error Amp Only) VMARGIN_ MAX1945S, VCOMP = 1V to 2V, VIN = 2.6V to 5.5V CTL1 = GND, CTL2 = VCC CTL1 = VCC, CTL2 = GND CTL1 = VCC, CTL2 = VCC CTL1 = GND, CTL2 = VCC CTL1 = VCC, CTL2 = GND FB Input Resistance FB Input Bias Current LX LX On-Resistance High LX On-Resistance Low LX Current-Sense Transresistance LX Current-Limit Threshold LX Leakage Current LX Switching Frequency LX Minimum Off-Time LX Maximum Duty Cycle ILEAK_LX fSW tOFF RON_
HIGH_LX
SYMBOL
CONDITIONS
MIN 1.773 2.462 0.788 6 -1.5 2.5 -5.5 -1.5 7.5 -10.5 25
TYP
MAX 1.827 2.538 0.812
UNITS
V A
VIN = 3.3V, VOUT = 1.8V, L = 1H
+1.5 5.5 -2.5 % +1.5 10.5 -7.5 100 0.1 43 50 43 50 k A
FB to GND, FBSEL = GND, or VFB = 1.8V, or FBSEL = VCC, or VFB = 2.5V FBSEL = High-Z, VFB = 0.7V VIN = VBST - VLX = 3.3V VIN = VBST - VLX = 2.6V VIN = 3.3V VIN = 2.6V From LX to COMP Duty cycle =100%, VIN = 2.6V/3.3V/5.5V VIN = 5.5V, CTL1 = CTL2 = GND VIN = 2.6V/3.3V VIN = 2.6V/3.3V VIN = 2.6V/3.3V SYNC = GND SYNC = VCC High side Low side VLX = 5.5V LX = GND SYNC = VCC SYNC = GND
m m m A A MHz kHz ns %
RON_ LOW_LX
43 8.0 -6 -100 0.8 400 90 80
65 12.8 -2 100 1.2 600 170
6
_______________________________________________________________________________________
1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VCC = VCTL1 = VCTL2 = VDD = 3.3V, SYNC = GND, FBSEL = High-Z, VFB = 0.7V, CREF = 0.22F, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER LX Minimum Duty Cycle FBSEL FBSEL Input Threshold 1.8V Where 1.8V feedback switches in and out, VCC = 2.6V/3.3V/5.5V Where 2.5V feedback switches in and out, VCC = 2.6V/3.3V/5.5V ILOW_
FBSEL
MAX1945R/MAX1945S
SYMBOL
CONDITIONS SYNC = VCC, VIN = 2.6V/3.3V
MIN
TYP
MAX 16
UNITS %
FBSEL rising FBSEL falling FBSEL rising FBSEL falling VCC 0.22 -50 0.08
0.22 V VCC 0.08
FBSEL Input Threshold 2.5V
V
FBSEL Input Current Low FBSEL Input Current High CTL1/CTL2 CTL1/CTL2 Input Threshold CTL1/CTL2 Input Current Soft-Start Period SYNC SYNC Capture Range SYNC Pulse Width SYNC Input Threshold SYNC Input Current SYNCOUT SYNCOUT Frequency Range
FBSEL = GND FBSEL = VCC
A 50 A
IHIGH_
FBSEL
VIL_CTL_ VIH_CTL_ IIL_CTL_ IIH_CTL_
VIN = 2.6V to 5.5V VCTL1 or VCTL2 = 0 or 5.5V, VIN = 5.5V Time required for output to ramp up VIN = 2.6V to 5.5V VIN = 2.6V to 5.5V
0.4 1.6 -1 -1 2.9 0.4 250 0.4 1.6 -1 0.4 VCC 0.4 +1 1.2 +1 +1 4.5 1.2
V A ms MHz ns V A MHz
VIL_SYNC VIH_SYNC IIL, IIH fSYNCOUT VOH_
SYNCOUT
VIN = 2.6V to 5.5V VSYNC = 0 or 5.5V, VIN = 5.5V VCC = 2.6V to 5.5V
SYNCOUT Output Voltage
VOL_
SYNCOUT
ISYNCOUT = 1mA, VCC = 2.6V to 5.5V
V 0.4
Note 2: Specifications to -40C are guaranteed by design, not production tested. Note 3: When connected together, the LX output is designed to provide 6A RMS current.
_______________________________________________________________________________________
7
1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators MAX1945R/MAX1945S
Typical Operating Characteristics
(VIN = VCC = 5V, VOUT = 1.8V, IOUT = 6A, fSW = 500kHz, VDD = VCC, and TA = +25C, unless otherwise noted.)
EFFICIENCY vs. OUTPUT CURRENT VIN = VCC = 5V
MAX1945 toc01
EFFICIENCY vs. OUTPUT CURRENT VIN = VCC = 3.3V
MAX1945 toc02
EFFICIENCY vs. OUTPUT CURRENT VIN = 2.5V, VCC = 5V
90 80 EFFICIENCY (%) 70 60 50 40 30 20 A B C
MAX1945 toc03
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 A: VOUT = 0.8V B: VOUT = 1.5V C: VOUT = 1.8V D: VOUT = 2.5V E: VOUT = 3.3V 1 2 3 4 A B C D E
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 A: VOUT = 0.8V B: VOUT = 1.5V C: VOUT = 1.8V D: VOUT = 2.5V 0 1 2 3 4 A B C D
100
VIN = VCC = 5V fSW = 500kHz 5 6 7
10 0
VIN = VCC = 3.3V fSW = 500kHz 5 6 7
10 0 0
A: VOUT = 0.8V B: VOUT = 1.5V C: VOUT = 1.8V 1 2 3
VIN = 2.5V, VCC = 5V fSW = 500kHz 4 5 6 7
IOUT (A)
IOUT (A)
IOUT (A)
REFERENCE VOLTAGE vs. REFERENCE SOURCE CURRENT
MAX1945 toc04
FREQUENCY vs. INPUT VOLTAGE (500kHz)
MAX1945 toc05a
FREQUENCY vs. INPUT VOLTAGE (1MHz)
MAX1945 toc05b
2.030 2.025 2.020 VREF (V) 2.015 2.010 2.005 fSW = 500kHz 2.000 0 4 8
550 540 530 FREQUENCY (kHz) 520 +25C 510 500 490 480 470 -40C +85C
1.050 1.025 FREQUENCY (MHz) 1.000 0.975 0.950 -40C 0.925 0.900 +85C +25C
12 16 20 24 28 32 36 40 IREF (A)
2.5
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
2.5
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
OUTPUT LOAD REGULATION
MAX1945 toc06
SHUTDOWN SUPPLY CURRENT vs. INPUT VOLTAGE
MAX1945 toc07
CURRENT LIMIT vs. OUTPUT VOLTAGE
13 12 CURRENT LIMIT (A) 11 10 9 8 7
MAX1945 toc08
3.0 2.5
fSW = 500kHz
14 12 10
14
2.5V VOUT (mV) 2.0 1.8V 1.5 1.0 0.8V 0.5 0 0 1 2 3 IOUT (A) 4 5 6 ISHDN (nA)
8 6 4 2 fSW = 500kHz 0 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5
fSW = 500kHz 6 0.8 1.3 1.8 2.3 2.8 3.3 VOUT (V)
8
_______________________________________________________________________________________
1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators
Typical Operating Characteristics (continued)
(VIN = VCC = 5V, VOUT = 1.8V, IOUT = 6A, fSW = 500kHz, VDD = VCC, and TA = +25C, unless otherwise noted.)
PGND-MEASURED TEMPERATURE vs. OUTPUT CURRENT
MAX1945 toc09
MAX1945R/MAX1945S
REFERENCE VOLTAGE vs. TEMPERATURE
MAX1945 toc10
OUTPUT SHORT-CIRCUIT CURRENT vs. INPUT VOLTAGE
OUTPUT SHORT-CIRCUIT CURRENT (A)
MAX1945 toc11
140 PGND-MEASURED TEMPERATURE (C) 120 100 80 60 40 20 0 6.0 VCC = VIN = 5V VOUT = 1.8V 6.5 7.0 AMBIENT TEMP: 0C 7.5 AMBIENT TEMP: +85C AMBIENT TEMP: +25C
2.030 2.025 2.020 VREF (V) 2.015 2.010 2.005 2.000
12 10 8 6 4 2 fSW = 500kHz 0
VIN = VCC = 5V fSW = 500kHz -40 -15 10 35 60 85 110 135
8.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
OUTPUT CURRENT (A)
TEMPERATURE (C)
INPUT VOLTAGE (V)
TRANSIENT RESPONSE VIN = 5V
MAX1945 toc12
TRANSIENT RESPONSE VIN = 3.3V
SWITCHING WAVEFORM VIN = 5V
MAX1945 toc13
MAX1945 toc14
VOUT 100mV/div 4.5A
VOUT 100mV/div 4.5A IOUT 1A/div 1.5A
VLX 5V/div
ILX 2A/div
IOUT 1A/div 1.5A
VOUT 100mV/div 400ns/div
20s/div
20s/div
STARTUP WAVEFORMS
MAX1945 toc15
SHUTDOWN WAVEFORMS
MAX1945 toc16
VOLTAGE MARGINING (4%)
MAX1945 toc17
VOUT 0.5V/div
VOUT 0.5V/div
VCTL1 2V/div
IIN 2A/div IIN, 2A/div VCTL1, CLT2 6A RESISTIVE LOAD 1ms/div 40s/div 200s/div VCTL1, VCTL2 VOUT 100mV/div
_______________________________________________________________________________________
9
1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators MAX1945R/MAX1945S
Typical Operating Characteristics (continued)
(VIN = VCC = 5V, VOUT = 1.8V, IOUT = 6A, fSW = 500kHz, VDD = VCC, and TA = +25C, unless otherwise noted.)
VOLTAGE MARGINING (9%)
MAX1945 toc18
SHORT-CIRCUIT INDUCTOR CURRENT
MAX1945 toc19
SHORT-CIRCUIT INDUCTOR CURRENT (EXPANDED TIME)
MAX1945 toc20
VCTL1 2V/div
VOUT 500mV/div
VOUT 500mV/div
ILX 10A/div VOUT 200mV/div ILX 5A/div
VLX 2V/div
400s/div
100ms/div
10s/div
Pin Description
PIN 1 2 3, 5, 7, 9, 20, 22, 24, 26 4, 6, 8, 10 11 12 13 14 NAME BST VDD LX FUNCTION Bootstrap Voltage. High-side driver supply input. Connect a 0.1F capacitor from BST to LX. Connect a Schottky diode from IN to BST. Low-Side Driver Supply Voltage Inductor Connection. Connect an inductor between LX and the regulator output. Connect all LX pins together close to the device. Power-Supply Voltage. Input voltage ranges from 2.6V to 5.5V. Bypass with 3 22F ceramic capacitors in parallel to PGND (see the Input Capacitor Selection section). Supply-Voltage Input. VCC powers the device. Connect a 10 resistor from IN to VCC. Bypass VCC to GND with 0.1F. Analog Ground Reference. Bypass REF with 0.22F capacitor to GND. REF tracks the soft-start ramp voltage margining and is pulled to GND when the output shuts down. Regulator Compensation. Connect a series RC network from COMP to GND. COMP is pulled to GND when the output shuts down (see the Compensation Design section). Feedback Input. When FBSEL = High-Z, use an external resistor divider from the output to set the voltage from 0.8V to 85% of VIN. Connect FB to the output for regulation to 1.8V when FBSEL = 0, or for regulation to 2.5V when FBSEL = VCC. Feedback Select Input. The device regulates to an output of 0.8V when FBSEL is left unconnected. The device regulates to an output of 1.8V when FBSEL = GND and regulates to an output of 2.5V when FBSEL = VCC. Synchronization/Frequency Select. Connect SYNC to GND for 500kHz operation, to VCC for 1MHz operation, or connect to an external clock at 400kHz to 1.2MHz. Synchronization Output. SYNCOUT provides a frequency output synchronized 180 degrees out-of-phase to the operating frequency of the device.
IN VCC GND REF COMP
15
FB
16
FBSEL
17 18
SYNC SYNCOUT
10
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1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators
Pin Description (continued)
PIN 19, 21, 23, 25 27 28 NAME PGND CTL1 CTL2 EP FUNCTION Power Ground. Connect all PGND together close to the device. Star connect GND to PGND (see the PC Board Layout Considerations section). Output Margining Control Inputs. When CTL1 = CTL2 = GND, the regulator is off. When CTL1 = CTL2 = VCC, the regulator runs at nominal output voltage. When CTL1 = VCC and CTL2 = GND, the output is set to the margin-low output (-4% or -9%). When CTL1 = GND and CTL2 = VCC, the output is set to the margin-high output (+4% or +9%). Exposed Pad. Connect to PGND to improve power dissipation.
MAX1945R/MAX1945S
Detailed Description
The MAX1945R/MAX1945S high-efficiency PWM switching regulators deliver up to 6A of output current. The devices operate at a selectable fixed frequency (500kHz or 1MHz) or can be synchronized to an external frequency (400kHz to 1.2MHz). The devices operate from a 2.6V to 5.5V input supply voltage and have a selectable output voltage of 1.8V or 2.5V, or an adjustable output voltage from 0.8V to 85% of the input voltage, making the MAX1945R/MAX1945S ideal for onboard post-regulation applications. The high switching frequency allows the use of small external components. Internal synchronous rectifiers improve efficiency and eliminate the typical Schottky freewheeling diode. Total output error over load, line, and temperature is less than 1%.
providing current to the output. The output capacitor stores charge when the inductor current exceeds the load current and discharges when the inductor current is lower, smoothing the voltage across the load. During an overload condition, when the inductor current exceeds the current limit (see the Current Limit section), the highside MOSFET does not turn on at the rising edge of the clock, and the low-side MOSFET remains on to let the inductor current ramp down.
Current Sense
An internal current-sense amplifier produces a current signal proportional to the voltage generated by the highside MOSFET on-resistance and the inductor current (RDS(ON) ILX). The amplified current-sense signal and the internal slope-compensation signal sum together at the comparator inverting input. The PWM comparator turns off the internal high-side MOSFET when this sum exceeds the COMP voltage from the error amplifier.
Controller Function
The MAX1945R/MAX1945S step-down converters use a PWM current-mode control scheme. A PWM comparator compares the integrated voltage-feedback signal against the sum of the amplified current-sense signal and the slope-compensation ramp. At each rising edge of the internal clock, the internal high-side MOSFET turns on until the PWM comparator trips. During this ontime, current ramps up through the inductor, sourcing current to the output and storing energy in the inductor. The current-mode feedback system regulates the peak inductor current as a function of the output voltage error signal. Because the average inductor current is nearly the same as the peak inductor current (<30% ripple current), the circuit acts as a switch-mode transconductance amplifier. To preserve inner-loop stability and eliminate inductor staircasing, a slope-compensation ramp is summed into the main PWM comparator. During the off-cycle, the internal high-side N-channel MOSFET turns off, and the internal low-side N-channel turns on. The inductor releases the stored energy as its current ramps down while still
Current Limit
The internal high-side MOSFET has a current limit of 8A (min). If the current flowing out of LX exceeds this limit, the high-side MOSFET turns off and the synchronous rectifier turns on. This lowers the duty cycle and causes the output voltage to droop until the current limit is no longer exceeded. The minimum duty cycle is limited to 10%. A synchronous rectifier current limit of 2A minimum protects the device from current flowing into LX. When the negative current limit is exceeded, the device turns off the synchronous rectifier, forcing the inductor current to flow through the high-side MOSFET body diode and back to the input, until the beginning of the next cycle, or until the inductor current drops to zero. The MAX1945R/MAX1945S use a pulse-skip mode to prevent overheating during short-circuit output conditions. The device enters pulse-skip mode when the FB voltage drops below 300mV, limiting the current and reducing power dissipation. Normal operation resumes upon removal of the short-circuit condition.
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11
1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators MAX1945R/MAX1945S
Soft-Start
The MAX1945R/MAX1945S employs digital soft-start to reduce supply in-rush current during startup conditions. When the device exits undervoltage lockout (UVLO), shutdown mode, or restarts following a thermal-overload event, the digital soft-start circuitry slowly ramps up the voltages at REF and FB (see the Typical Operating Characteristics). An internal oscillator sets the soft-start time to 3.7ms (typ). Use a of 0.22F capacitor (min) to reduce the susceptibility to switching noise.
Shutdown Mode
Drive CTL1 and CTL2 to ground to shut down the MAX1945R/MAX1945S. In shutdown mode, the internal MOSFETs stop switching and LX goes to high impedance; REF and COMP go to ground.
Voltage Margining
The MAX1945R/MAX1945S provide selectable voltage margining. The MAX1945R provides 4% voltage margining, and the MAX1945S provides 9% voltage margining. CTL1 and CTL2 set the voltage margins (Table 1).
Undervoltage Lockout (UVLO)
When VCC drops below 2.35V, the UVLO circuit inhibits switching. Once VCC rises above 2.4V, UVLO clears and the soft-start function activates.
Table 1. Setting Voltage Margin
CTL1 0V Voltage Margin VCC VCC 0V CTL2 0V VCC 0V VCC VOUT MAX1945R OFF NOMINAL -4% +4% MAX1945S OFF NOMINAL -9% +9%
Bootstrap (BST)
A capacitor connected between BST and LX and a Schottky diode connected from IN to BST generate the gate drive for the internal high-side N-channel MOSFET. When the low-side N-channel MOSFET is on, LX goes to PGND. IN charges the bootstrap capacitor through the Schottky diode. When the low-side N-channel MOSFET turns off and the high side N-channel MOSFET turns on, VLX goes to VIN. The Schottky diode prevents the capacitor from discharging into IN.
Thermal Protection
Thermal-overload protection limits total power dissipation in the device. When the junction temperature (TJ) exceeds 165C, a thermal sensor forces the device into shutdown, allowing the die to cool. The thermal sensor turns the device on again after the junction temperature cools by 20C, causing a pulsed output during continuous overload conditions.The soft-start sequence begins after a thermal-shutdown condition.
Frequency Select (SYNC)
The MAX1945R/MAX1945S operate in PWM mode with a selectable fixed frequency or synchronized to an external frequency. The devices switch at a frequency of 500kHz when SYNC is connected to ground. The devices switch at 1MHz with SYNC connected to VCC. Apply an external frequency of 400kHz to 1.2MHz with 10% to 90% duty cycle at SYNC to synchronize the switching frequency of MAX1945R/MAX1945S.
Design Procedure
VCC Decoupling
Because of the high switching frequency and tight output tolerance, decouple VCC with 0.1F capacitor from VCC to GND with a 10 resistor from VCC to IN. Place the capacitor as close to VCC as possible.
Output Voltage Select
The MAX1945R/MAX1945S feature selectable fixed and adjustable output voltages. With FB connected to the output, the output voltage is 1.8V when FBSEL is at GND and 2.5V when FBSEL is at VCC (Figure 1). When FBSEL is floating, connect FB to an external resistor divider from V OUT to GND to set the output voltage from 0.8V to 85% of VIN (Figure 2). Select R2 in the 1k to 10k range. Calculate R1 using the following equation: V R1 = R2 OUT VFB where VFB = 0.8V.
-
Inductor Design
Choose an inductor with the following equation: L= VOUT x
1
fOSC x VIN x LIR x IOUT(MAX)
(VIN - VOUT )
where LIR is the ratio of the inductor ripple current to average continuous current at a minimum duty cycle. Choose LIR between 20% to 40% of the maximum load current for best performance and stability.
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1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators
Use a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. Ferrite core types are often the best choice for performance. With any core material the core must be large enough not to saturate at the peak inductor current (IPEAK). LIR IPEAK = 1 + IOUT(MAX) 2 Example: VIN = 3.3V VOUT = 1.8V fOSC = 500kHz IOUT(MAX) = 6A LIR = 30% L = 1H and IPEAK = 6.9A IOUT(MAX) = 6A LIR = 30% L = 1H COUT = 180F ESR(OUTPUT CAPACITOR) = 30m ESL(OUTPUT CAPACITOR) = 2.5nH VRIPPLE(C) = 2mV VRIPPLE(ESR) = 45mV VRIPPLE(ESL) = 4mV VRIPPLE = 51mV Use these equations for initial capacitor selection. Determine final values by testing a prototype or an evaluation circuit. A smaller ripple current results in less output voltage ripple. Because the inductor ripple current is a factor of the inductor value, the output voltage ripple decreases with a larger inductance. Use ceramic capacitors for low ESR and low ESL at the switching frequency of the converter. The low ESL of ceramic capacitors makes ripple voltages negligible. Load transient response depends on the selected output. During a load transient, the output instantly changes by ESR ILOAD. Before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. After a short time (see the Transient Response graphs in the Typical Operating Characteristics), the controller responds by regulating the output voltage back to its predetermined value. The controller response time depends on the closed-loop bandwidth. A higher bandwidth yields a faster response time, preventing the output from deviating further from its regulating value.
MAX1945R/MAX1945S
Output Capacitor Selection
The key selection parameters for the output capacitor are capacitance, ESR, ESL, and voltage rating requirements. These affect the overall stability, output ripple voltage, and transient response of the DC-DC converter. The output ripple occurs because of variations in the charge stored in the output capacitor, the voltage drop due to the capacitor's ESR, and the voltage drop due to the capacitor's ESL. Calculate the output voltage ripple due to the output capacitance, ESR, and ESL as: VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL) where the output ripple due to output capacitance, ESR, and ESL are: VRIPPLE(C) = IP-P/(8 COUT fSW), VRIPPLE(ESR) = IP-P ESR VRIPPLE(ESL) = (IP-P/tON) ESL or (IP-P/tOFF) ESL, whichever is greater The peak inductor current (IP-P) is: IP-P = ((VIN - VOUT)/(fSW L )) (VOUT/VIN) Example: VIN = 3.3V VOUT = 1.8V fOSC = 500kHz
Input Capacitor Selection
The input capacitor reduces the current peaks drawn from the input power supply and reduces switching noise in the IC. The impedance of the input capacitor at the switching frequency should be less than that of the input source so that high-frequency switching currents do not pass through the input source but instead are shunted through the input capacitor. A high source impedance requires larger input capacitance. The input capacitor must meet the ripple current requirement imposed by the switching currents. The RMS input ripple current is given by: V x (VIN - VOUT ) OUT IRIPPLE = ILOAD x VIN where IRIPPLE is the input RMS ripple current.
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1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators MAX1945R/MAX1945S
Compensation Design
The double pole formed by the inductor and the output capacitor of most voltage-mode controllers introduces a large phase shift, which requires an elaborate compensation network to stabilize the control loop. The MAX1945R/MAX1945S controllers utilize a currentmode control scheme that regulates the output voltage by forcing the required current through the external inductor, eliminating the double pole caused by the inductor and output capacitor, and greatly simplifying the compensation network. A simple Type 1 compensation with a single compensation resistor (RC) and compensation capacitor (CC) creates a stable and high bandwidth loop (Figure 1). An internal transconductance error amplifier compensates the control loop. Connect a series resistor and capacitor between COMP (the output of the error amplifier) and GND, to form a pole-zero pair. The external inductor, internal current-sense circuitry, output capacitor, and external compensation circuit determine the loop-system stability. Choose the inductor and output capacitor based on performance, size, and cost. Additionally, select the compensation resistor and capacitor to optimize control-loop stability. The component values shown in the typical application circuit yield stable operation over a broad range of input-to-output voltages. Compensating the voltage feedback loop depends on the type of output capacitors used. Common capacitors for output filtering: ceramic capacitors, polymer capacitors such as POSCAPs and SPCAPs, and electrolytic capacitors. Use either ceramic or polymer capacitors. Use polymer capacitors as the output capacitor when selecting 500kHz operation. At 500kHz switching, the voltage feedback loop is slower (about 50kHz to 60kHz) when compared to 1MHz switching. Therefore, a polymer capacitor's high capacitance for a given footprint improves the output response during a step load change. Because of its relative low ESR frequencies (about 20kHz to 80kHz), use Type 2 compensation. The additional high-frequency pole introduced in Type 2 compensation offsets the ESR zero introduced by the polymer capacitors to provide continuous attenuation above the ESR zero frequencies of the polymer capacitors. However, the presence of the parasitic capacitance at COMP and the high output impedance of the error amplifier already provide the required attenuation above the ESR frequencies. The following steps outline the design process of compensating the MAX1945 with polymer output capacitors with the components in the application circuits Figures 1 and 2. Regulator DC Gain: GDC = VOUT/VCOMP = gmc ROUT Load Impedance Pole Frequency: fpLOAD = 1/(2 COUT (ROUT + RESR)) Load Impedance Zero Frequency: fzESR = 1/(2 COUT RESR) where ROUT = VOUT/IOUT(MAX), and gmc = 18.2S. The feedback divider has a gain of GFB = VFB/VOUT, where VFB = 0.8V. The transconductance error amplifier has a DC gain, GEA(DC), of 70dB. The compensation capacitor, CC, and the output resistance of the error amplifier, ROEA (20M), set the dominant pole. CC and RC set a compensation zero. Calculate the dominant pole frequency as: fp = 1/(2 CC ROEA) Determine the compensation zero frequency as: fzEA = 1/(2 CC RC) For best stability and response performance, set the closed-loop unity-gain frequency much higher than the load-impedance pole frequency. The closed-loop unitygain crossover frequency must be less than one-fifth of the switching frequency. Set the crossover frequency to 10% to 15% of the switching frequency. The loop-gain equation at unity-gain frequency, fC, is given by: GEA GDC (fPLOAD/fC) (VFB/VOUT) = 1 where G EA = gm EA R C , and gm EA = 50S, the transconductance of the voltage-error amplifier. Calculate RC as: RC = (VOUT fC)/(gmEA VFB GDC fPLOAD)
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1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators
Set the error-amplifier compensation zero formed by RC and CC equal to the load-impedance pole frequency, fPLOAD, at maximum load. Calculate CC as: CC = (COUT ROUT)/RC 500kHz Switching The following design example is for the application circuit shown in Figures 1 and 2: VOUT = 1.8V IOUT(MAX) = 6A COUT = 180F RESR = 0.04 gmEA = 50s gmc = 18.2s fSWITCH = 500kHz ROUT = VOUT/IOUT(MAX) = 1.8V/6 A = 0.3 fpDC = 1/(2 COUT (ROUT + RESR) = 1/(2 180 10-6 (0.3 + 0.04) = 2.6kHz. fzESR = 1/(2 COUT RESR) = 1/(2 180 10-6 0.04) = 22.1kHz. Pick the closed-loop unity-gain crossover frequency (fc) at 60kHz. Determine the switching regulator DC gain: GDC = gmc ROUT = 18.2 0.3 = 5.46 then: RC = (VOUT fC)/(gmEA VFB GDC fpLOAD) = (1.8 60kHz)/(50 10-6 0.8 5.46 2.6kHz) 190k (1%), choose RC = 180k, 1% CC = (COUT (ROUT + RESR))/RC = (180uF (0.3 + 0.04))/180k 340pF, choose CC = 330pF, 10% Table 2 shows the recommended values for RC and CC for different output voltages. 1MHz Switching Following procedure outlines the compensation process of the MAX1945 for 1MHz operation with all ceramic output capacitors (Figure 3). The basic regulator loop consists of a power modulator, an output-feedback divider, and an error amplifier. The switching regulator has a DC gain set by gmc ROUT, where gmc is the transconductance from the output voltage of the error amplifier to the output inductor current. The load impedance of the switching modulator consists of a pole-zero pair set by R OUT , the output capacitor (COUT), and its ESR. The following equations define the power train of the switching regulator: Regulator DC Gain: GDC = VOUT/VCOMP = gmc ROUT Load-Impedance Pole Frequency: fpLOAD = 1/(2 COUT (ROUT +RESR)) Load-Impedance Zero Frequency: fzESR = 1/(2 COUT RESR) where, ROUT = VOUT/IOUT(MAX), and gmc = 18.2. The feedback divider has a gain of GFB = VFB/VOUT, where VFB is equal to 0.8V. The transconductance error amplifier has a DC gain, GEA(DC), of 70dB. The compensation capacitor, CC, and the output resistance of the error amplifier, ROEA (20M), set the dominant pole. C C and R C set a compensation zero. Calculate the dominant pole frequency as: fpEA = 1/(2 CC ROEA) Determine the compensation zero frequency as: fzEA = 1/(2 CC RC) For best stability and response performance, set the closed-loop unity-gain frequency much higher than the load impedance pole frequency. In addition, set the closed-loop unity-gain crossover frequency less than one-fifth of the switching frequency. However, the maxi-
MAX1945R/MAX1945S
Table 2. Compensation Values for Output Voltages (500kHz)
VOUT (V) RC CC 0.8 110k 330pF 1.2 147k 330pF 1.8 180k 330pF 2.5 287k 220pF 3.3 365k 220pF
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15
1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators MAX1945R/MAX1945S
Table 3. Compensation Values for Output Voltages (1MHz)
VOUT (V) RC (1%) CC (10%) 0.8 100k 330pF 1.2 100k 330pF 1.8 178k 100pF 2.2 178k 100pF 3.3 249k 100pF
mum zero-crossing frequency should be less than onethird of the load-impedance zero frequency, fzESR. The previous requirement on the ESR zero frequency applies to ceramic output capacitors. The loop-gain equation at unity-gain frequency, fC, is given by: GEA(fc) GDC (fPLOAD/fC) (VFB/VOUT) = 1 where G EA(fc) = gm EA R C , and gm EA = 50, the transconductance of the voltage error amplifier. Calculate RC as: RC = (VOUT fC)/(gmEA VFB GDC fPLOAD) Set the error-amplifier compensation zero formed by RC and CC equal to the load-impedance pole frequency, fPLOAD, at maximum load. Calculate CC as follows: CC = (COUT ROUT)/RC
As the load current decreases, the load-impedance pole also decreases; however, the switching regulator DC gain increases accordingly, resulting in a constant closed-loop unity-gain frequency. Table 3 shows the values for RC and CC at various output voltages. The values are based on 2 47F output capacitors and a 0.68H output inductance. For COUT = 2 47F and L = 0.68H. Decrease RC accordingly when using large values of COUT or L. VOUT = 1.8V IOUT(MAX) = 6A COUT = 2 47F RESR = 0.005 gmEA = 50 gmc = 18.2s fSWITCH = 1.0MHz ROUT = VOUT/IOUT(MAX) = 1.8V/6A= 0.3 fpDC = [1/(2 COUT (ROUT + RESR))] = [1/(2 94 10-6 (0.3 + 0.005))] = 5.554kHz
Applications Information
BAT54A 0.1F 10V BAT54A 1H INPUT: 2.6V TO 5.5V 100F 8V RIN BST IN VDD LX OUTPUT: 1.8V, 6A INPUT: 2.6V TO 5.5V 100F 8V RIN BST IN VDD LX 1H VOUT 180F 4V PGND R1 SYNCOUT CTL2 RC COMP 0.22F 10V CC FB FBSEL R2 REF GND REF SYNC GND 0.22F 10V 0.1F 10V
VCC CIN RC COMP CC FBSEL CTL1 CTL2
MAX1945R MAX1946S
PGND
180F 4V
MAX1945R MAX1946S
VCC CIN CTL1
FB SYNCOUT
SYNC
Figure 1. Typical Application Circuit (Fixed Output Voltage)
Figure 2. Typical Application Circuit (Adjustable Output Voltage)
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1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators
fzESR = [1/(2 COUT RESR)] = [1/(2 94 10-6 0.005)] = 339kHz. For a 0.68H output inductor, choose the closed-loop unity-gain crossover frequency (f c ) at 120kHz. Determine the switching regulator DC gain: GDC = gmc ROUT = 18.2 0.3 = 5.46 then: RC = (VOUT fC)/(gmEA VFB GDC fpLOAD) = (1.8 120kHz)/(50 10-6 0.8 5.46 5.554kHz) 178k (1%) CC = (COUT ROUT)/RC =(94F 0.3)/178k 156pF, choose CC = 100pF, 10% Output Inductor: 0.68H/12A, 5m ESR (max), Coilcraft DS3316P-681 Output Capacitor C5: 2XJMK432BJ476MM Input Capacitor C1: LMK432BJ226MM
PC Board Layout Considerations
Careful PC board layout is critical to achieve clean and stable operation. The switching power stage requires particular attention. Follow these guidelines for good PC board layout: 1) Place decoupling capacitors as close to the IC as possible. Keep power ground plane (connected to PGND) and signal ground plane (connected to GND) separate. Star connect both ground plane at output capacitor. 2) Connect input and output capacitors to the power ground plane; connect all other capacitors to the signal ground plane. 3) Keep the high-current paths as short and wide as possible. Keep the path of switching current short and minimize the loop area formed by the high-side MOSFET, the low side MOSFET, and the input capacitors. Avoid vias in the switching paths. 4) Connect IN, LX, and PGND separately to a large copper area to help cool the IC to further improve efficiency and long-term reliability. 5) Ensure all feedback connections are short and direct. Place the feedback resistors as close to the IC as possible.
MAX1945R/MAX1945S
VCC = 3.3V OR 5V
C4 1F IN IN IN VIN = 2.5V IN R1 10 C1 3 x 22F LX VDD VCC LX LX LX CTL1 CTL2 C6 0.1F SYNCOUT LX LX FB BST
D1 C3 0.1F
6) Route high-speed switching nodes away from sensitive analog areas (FB, COMP).
MAX1945R MAX1945S
LX LX L1 0.68F 1.8V, 6A
Chip Information
TRANSISTOR COUNT: 5000 PROCESS: BiCMOS
SYNC COMP REF FBSEL
C5 2 x 47F
PGND
PGND
PGND
PGND
RC 178k
GND
CC 100pF GND
C4 0.22F PGND
Figure 3. Typical Application Circuit with all ceramic capacitors (1MHz) ______________________________________________________________________________________ 17
1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators MAX1945R/MAX1945S
Functional Diagram
IN
BST N SYNCOUT AC DETECT SYNC CTL1 CONTROL CTL2 VCC 8 COUNT (8 BIT) N PGND OSCILLATOR PWM CONTROL LOGIC LX VDD
REFERENCE GND
8 BIT DAC
2X
REF
3R COMP FB FB FBSEL EAMP 2R
MAX1945R MAX1945S
Pin Configuration
TOP VIEW
BST 1 VDD 2 LX 3 IN 4 LX 5 IN 6 LX 7 IN 8 LX 9 IN 10 VCC 11 GND 12 REF 13 COMP 14 28 CTL2 27 CTL1 26 LX 25 PGND 24 LX
MAX1945R MAX1945S
23 PGND 22 LX 21 PGND 20 LX 19 PGND 18 SYNCOUT 17 SYNC 16 FBSEL 15 FB
28 TSSOP-EP
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1MHz, 1% Accurate, 6A Internal Switch Step-Down Regulators
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP, 4.0,EXP PADS.EPS
MAX1945R/MAX1945S
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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